1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a ferroelectric memory comprising memory cells each containing a ferroelectric capacitor and a transistor.
2. Description of the Related Art
A ferroelectric memory (FeRAM) is such a semiconductor memory device that utilizes the hysteresis characteristic of a ferroelectric capacitor to store data nonvolatile in accordance with magnitudes of two different polarized states of the ferroelectric.
A memory cell in the conventional ferroelectric memory generally uses the architecture similar to that of a DRAM, which comprises a ferroelectric capacitor replaced with a paraelectric capacitor, and a selection transistor serially connected to the ferroelectric capacitor (see JP 2001-250376A, for example). Plural such memory cells are arranged in grid to configure a memory cell array. In data reading, a word line (selection line) associated with a memory cell targeted for read is activated by turning on a selection transistor to connect the memory cell to a bit line.
A cell transistor and a ferroelectric memory are connected in parallel to configure one memory cell and such memory cells are serially connected to configure a memory cell block in a ferroelectric memory of the so-called TC parallel unit serial connection type as known (see JP 2005-4811A, for example). In the ferroelectric memory of the TC parallel unit serial connection type, each memory cell block can be connected to a bit line when a block selection transistor having a gate connected to a block selection line (selection line) turns on.
In either the DRAM-analogous structure or the structure of the TC parallel unit serial connection type, the ferroelectric memory may adopt a 2-transistor/2-cell system (2T2C system) that uses two memory cells for reading complementary data, and a 1-transistor/1-cell system (1T1C system) that uses one memory cell for reading.
One having the DRAM-analogous structure is described by way of example. In the 2T2C system, the word line connected to a read-targeted memory cell and the word line associated with a complementary memory cell that holds complementary data are selected to connect the memory cell to a bit line and the complementary memory cell to a complementary bit line.
Thereafter, a plate voltage is applied to a plate line, and a voltage is applied across the ferroelectric capacitors contained in the read-targeted and complementary memory cells. The charge on the ferroelectric capacitor in the memory cell is read out to the bit line while the charge on the ferroelectric capacitor in the complementary memory cell is read out to the complementary bit line. The potentials on the paired bit lines are compared and amplified at a sense amp.
In the 1T1C system, on the other hand, the word line connected to a read-targeted cell is selected to connect the memory cell to a bit line. Thereafter, a plate voltage is applied to a plate line connected to the memory cell, and a voltage is applied across the ferroelectric capacitor contained in the memory cell.
The charge on the ferroelectric capacitor in the memory cell is read out to the bit line while a reference voltage is generated from a reference voltage generator and applied to a complementary bit line paired with the bit line. The potentials on the paired bit lines are compared and amplified at a sense amp. The TC parallel unit serial connection type is also similar to the above except that a block selection transistor is used to select a memory cell block and a word line to select a memory cell.
The 1T1C system and the 2T2C system have respective advantages and disadvantages. Therefore, it is preferable if one ferroelectric memory can be configured to execute the 1T1C system and the 2T2C system selectively. JP2005-4811A proposes such the ferroelectric memory.
The selective execution of the 1T1C system and the 2T2C system requires two selection transistors (or block selection transistors) configured independently drivable for selecting a bit line pair. An execution of the 1T1C system requires one of the complementary bit lines used in data reading and the other used as a shield line.
Therefore, selection of a pair of bit lines requires the preparation of a set of (two) word lines paired, thereby causing an increase in the area of the memory cell array and thus the chip area.